Electronic correction

ABSTRACT

An electronic time-piece is advanced by electronic pulses which are generated by a fixed frequency signal source. In order to correct the indication of the time-piece, a circuit is provided for adding or deleting pulses to thereby increment or decrement the indication. One push-button switch is provided for both adding or subtracting seconds from the indication displayed by the time-piece. Each depression of the push-button adds one second to the indication. When the user depresses the push-button and holds it depressed, one second is initially added to the indication, and then further transmission of electronic pulses is blocked so that the user may effectively subtract as many seconds as necessary from the displayed indication.

United States Patent [191 Sauthier [4 1 Dec. 10-, 1974 ELECTRONIC CORRECTION [75] Inventor: Pierre Sauthier, Bienne, Switzerland [73] Assignee: Societe Suisse Pour LIndustrie Horlogere Management Services S.A., Bienne, Switzerland [22] Filed: July 12, 1973 [21] Appl. No.: 378,627

[30] Foreign Application Priority Data July 12, 1972 Great Britain 32577/72 [52] US. Cl. 58/23 R, 58/85.5 [51] Int. Cl. G040 3/00, G04b 27/00 [58] Field Of Search 58/23 R, 85.5

[56] 4 I References Cited UNITED STATES PATENTS 3,672,155 6/1972 Bergey et al. 58/50 R 3,765,163 10/1973 Levine et al. 58/23 A X Primary Examiner-Edith Simmons Jackmon Attorney, Agent, or Firm Griffin, Branigan and Butler [5 7] ABSTRACT An electronic time-piece is advanced by electronic pulses which are generated by a fixed frequency signal source. In order to correct the indication of the timepiece, a circuit is provided for adding or deleting pulses to thereby increment or decrement the indication. One push-button switch is provided for both adding or subtracting seconds from the indication displayed by the time-piece. Each depression of the pushbutton adds'o'ne second to the indication. When the user depresses the push-button and holds it depressed, one second is initially added to the indication, and then further transmission of electronic pulses is blocked so that the user may effectively subtract as many seconds as necessary from the displayed indication.

PATENTED um 10 mm sum 2 or 5 L JI QQ EQQQ v l l m PATENTEUUEU 10 m4 SHEET 5 OF 5 \III 1 ELECTRONIC CORRECTION This invention provides an addition and an improvement to the invention described in my commonly assigned application Ser. No. 312,328 filed Dec, 5, 1972 and which is now US. Pat. No. 3,786,625. In the earlier patent application has been disclosed a control arrangement for setting the seconds indicator in timepieces of the quartz crystal variety. The earlier arrangement was generally concerned with preventing coincidences between signals originating from the timekeeping standard and supplemental signals externally applied by the user.

Two separate control switches were shown, one of which when operated, added a single count to the seconds display and the other of which, when actuated, subtracted a single count from the seconds display.

The advantage of the present invention from the viewpointat least of the user is that both addition and subtraction of seconds to or from the display may be effected by a single control switch which may take the form of a push-button for example. Thus to add seconds the user pushes the button once for each second he desires to add. To subtract seconds the user pushes the button and holds it depressed whereupon initially a second is added and thereafter further transmission of signals from the time standard to the display are blocked so that the user may subtract as many seconds from the indication of the display as circumstances warrant.

Accordingly, the invention provides a time-piece in which a time standard supplies signals of a predetermined frequency to a first sequence of bistable devices arranged and adapted to provide output signals ofa desired frequency to a display arrangement in which at least seconds are displayed, wherein means are provided to set the seconds display through the supplying of additional output signals or the withholding of output signals, said means including a complement output terminal on at leastone of the bistable devices in the first sequence, a bistable storage device arranged to be manually switchable to a first stable state and to be automatically restored to a second stable state by signals obtained from the complement Output terminal, a display control toggle having an input arrangement which logically combines said output signals from the first sequence of bistable devices with signals from the bistable storage device, a delaycircuit having a controllable disabling switch and receiving an input from a predetermined bistable device in the first sequence in order to provide an output adapted to block signal transmission from at least one bistable device in the first sequence and a manually operable switch coupled to the bistable storage device and the delay circuit disabling switch, the arrangement being such that actuation of the switch for a time period less than that of the delay circuit adds one signal to the seconds display and actuation of the switch for a greater time period adds one signal and thereafter blocks transmission of further signals to the seconds display for as long as the switch continuesto be actuated.

For a better understanding of the invention reference will now be had to the accompanying drawings in which FIG. 1 represents a schematic lay-out of the logic of ing of the present invention and FIG. 2 is a timing diagram relating to the transmission of signals in the circuit of FIG. 1,

FIG. 3 represents a simplified variant of the version of the invention shown in FIG. 1,

FIG. 4 is a timing diagram relating to FIG. 3,

FIG. 5 shows a typical circuit which might be used for the bistable devices in the counter sequences.

The basic arrangement is similar to that of FIG. 1 of my above mentioned earlier patent application in so far as the addition of seconds is concerned. The present invention however shows one of the more difficult arrangements in which a stepping motor is used to drive the display and the stepping motor requires successive drive pulses of opposite polarity. The stepping motor is arranged in a conventional manner to drive time indicating hands. It will be however obvious that the principle of the correction control as taught by the present patent application is equally applicable to a less complex situation which may be provided by other displays.

In the present case the motor control circuit must provide a change of direction of the current in the winding at each step. For this arrangement it is impractical to add or subtract pulses through acting directly on the motor winding. Thus the operation to be carried out acts on the logic. As has been shown in my earlier application one may add a pulse to the motor for each actuation of the switch. There remains to be described an arrangement which permits, following a predetermined delay period, the suppression of current pulses. Such delay should be greater than the time necessary for theaddition ofa second by a normal actuation of the switch, but as short as possible and in any event shorter than 1 second. A reasonable delay would seem to be from A to /2 a second.

The realization of such delay T may be effected by analogue methods (integration ofa current in a capacitor) or digital methods (counters). The first solution would require for the necessary delays and currents,

non-integratable capacitors and this will constitute a disadvantage in the case of Wristwatches. The digital technique of employing a series of counters is as illustrated in FIG. 1. While such an arrangement may seem in fact quite complex it may nevertheless be easily added in the course of manufacturing the remainder of the circuit by integrated circuit techniques.

As soon as the delay T has been exceeded it is necessary to suppress current pulses and this must be effected before the last bistable stage (16) which effectively remembers the direction of the last current pulse in the winding is switched. Several methods are possible of which certain are better adapted than others according to the chosen integration technique. ()ne such method may utilize the clamping of certain stages in the frequency divider thus one stage may be clamped during a time period extending from t =t T (where 1,, represents the moment that the switch is actuated and T represents the delay prior to inhibition) until t (representing the moment that the switch is released).

During the period I, stage 11 as shown for purposes of illustration in FIG. 1 is clamped and this suspends the counting action of stages further down the chain and thus suppresses current pulses in the motor.

Since actuation of the switch P will in any event add one second it will be necessary to wait n 1 seconds in order to subtract n-seconds. The reliability of the arrangement depends partly on the user and particularly 1. from the moment between two normal pulses from the time standard when he actuates the switch when he wishes to subtract seconds and 2. the duration of his actuation of the switch when he wishes to add seconds.

In the first instance if he actuates the switch in an interval T before a normal pulse this will bring about a first addition of one second at the moment when he operates the switch and a second addition of 1 second at the moment of the normal pulse. Since this takes place in the delay T preceding inhibition of the motor pulses such actuation may thus hinder exact setting.

In the second case actuation for a delay greater than T will inhibit the 1 1th stage and thus cause loss of the exact phase of the second. This may be however unimportant if the total duration of the switch actuation is only slightly greater than T when one wishes to add seconds.

One may equally select the last five stages of the divider which will effectively enable a more precise setting since the first current pulse will arrive exactly 1 second after the release of the switch. This arrangement may however present a disadvantage should one wish to effect a simple subtraction of seconds. Thus resetting the last five stages will bring about a change of state of the last stage 16 should it be in its odd stateO which will have as an effect the addition of a 2nd secnd at the end of T This second addition is not foreseeable and for this reason causes greater difficulty since it is necessary to observe and count the added seconds" in order to calculate the subtraction time which might thus be n l or n 2 in order to subtract n-seconds. Such a difficulty will practically never appear when only one of the stages is clamped on condition that such stage be at a relatively high frequency.

The arrangement as shown in FIG. 1 provides stages 9 to 18, earlier stages not being illustrated. Stage 9 in this particular arrangement would receive signals at a frequency of 128 Hz from the preceding part of the divider and stages 17 and 18 are set and reset alternately each second in order to control complementary transistor pairs 8;; S S S which in turn deliver pulses of alternatingdirection to the motor winding M.

Push-button P may be followed by an integrator stage I which is intended to suppress the electrical effect of the mechanical irregularities (bounces) of the pushbutton. One actuation of push-button P will change the output state 6 of bistable storage device 19 from one to zero. This change .will have no effect on stage 16 since the type of circuit employed reacts only to positive-going pulses and it is only upon the arrival of a complement output from stage 12 that stage 19 thereafter produces a one-output to change the state of toggle 16 and subsequently add I second to the display. This part of the circuit will be seen to be practically identicalwith that shown in my earlier patent application. The output signal from the push-button P following the integration stage I is also passed across an inverter N and it will be seen that normally the output from N will be a positive signal which serves to saturate transistor T and thereby disable the secondary sequence of dividers 20, 21, 22 and 23. When however push-button P is actuated the output from inverter N will block transistor T, and stages 20, 21, 22 and 23 will no longer be inhibited. These stages will thus commence to count signals received from stage 10. During this time the leading edge of the the signalYfrom the complement output of stage 12 will have changed the state of bistable storage device 19 thereby, as previously explained, bringing about addition of I second to the display.

If the push-button is released before T i.e., before the time that stage 24 has changed its state then stages 20, 21, 22 and 23 will be reset to zero and the main divider (stages 9 to 18 as shown) will not be affected. Should however the push-button be actuated longer than T transistor T will saturate at the end of the delay period T and will remain saturated until the push-button P is released. When such release is effected it will cause a positive output from N thereby resetting stage 24 to zero and blocking stages 20, 21, 22 and 23. As long as T remains saturated stage 11 will be clamped. When stage 24 is reset, transistor T is switched off and stage 11 resumes its normal function.

In integrated circuit technology such as complementary MOS it is possible to implant logical gates and in such instances the inhibition of stage 11 may be replaced by an AND-gate between stage 10 and stage 11 which will be enabled or disabled according to the state of stage 24, transistor T in this case being eliminated.

In order to set the phase exactly, as previously suggested a circuit utilizing a switch SW, resistor R and transistor T may be used to clamp the last five stages of the divider circuit through actuation of, for example, the crown of the time-piece. When the switch SW is released the next motor pulse follows 1 second later.

The timing of the various switching changes for this version of the correction circuit is as illustrated in FIG. 2 in which the symbols Q represent outputs from the bistable stages. Accordingly. 6 represents complement outputs, P represents the actuation of the push-button P and I represents motor impulses. The dotted representations are those which would occur in the normal state of operation, i.e., in the event that the pushbutton was not actuated.

FIG. 3 shows a simplified version of the invention which has actually been reduced to practice. Reference numbers relating to similar elements are the same in both FIGS. 1 and 3. For a further simplification of the drawing transistors are not shown as such, but it will be understood for example that the switches S and S would comprise transistors according to the chosen integration technique. Elements not essential to the understanding of the logic have been omitted and the motor circuits are simply shown as a block M.

The principal difference between FIG. 1 and FIG. 3 lies in the fact that only two dividers 20 and 21 are shown in the secondary sequence 21. These are provided with a self-latching circuit S the effect of which is to eliminate the need for the memory stage 24 of FIG. 1.

As in the case of FIG. 1 actuation of push-button P sets flip-flop l9 hereby adding one signal to the display via toggle l6 and flip-flop l7 and 18. At the same time switch S is opened by means of inverter stage N thereby enabling stages 20 and 21 to begin counting. It will b e observed that the input to stage 20 is taken from the Q output of stage 13 which will be at a frequency of 4 Hz. In the FIG. l-version the input of stage 20 was at 32 Hz. Thus the delay period T}; ends with the second leading edge signal of the output of stage 13 and I it is evident that T will be at least A second and at most /2 second. If the push-button is held down longer than T switch S is closed at the end of the delay period T and will remain closed until the push-button P is released. When P is released it will cause a positive output from N hereby clamping stages 19 and 20 and thus opening switch S This permits stage 13 to resume its normal function.

I Timing of the circuit as shown in FIG. 3 is illustrated in FIG. 4 in which the suppressed motor pulses are shown by means of dotted outlines.

FIG. 5 shows how part of the logic of FIG. 3 might be actually realized and it will be appreciated from the nature of the bistable stages why it is that setting of the switch S will result in clamping bistable stage 13. When the normal output from the reset side is held at ground, it is obvious that no changes will occur from the other output so that the normal counting action is blocked.

What I claim is:

1. Time-piece in which a time standard supplies signals of a predetermined frequency to a first sequence of bistable devices arranged and adapted to provide output signals of a desired frequency to a display arrangement in which at least seconds are displayed, wherein means are provided to set the seconds display through the supplying of additional output signals or the withholding of output signals, said means including a complement output terminal on at least one of the bistable devices in the first sequence, a bistable storage device arranged to be manually switchable to a first stable state and to be automatically restored to'a second stable state by signals obtained from the complement output terminal, a display control toggle having an input arrangement which logically combines said output signals from the first sequence of bistable devices with signals from the bistable storage device, a delay circuit having a controllable disabling switch and receiving an input from a predetermined bistable device in the first sequence in order to provide an output adapted to block signal transmission from at least one bistable device in the first sequence; and a manually operable switch coupled to the bistable storage device and the delay circuit disabling switch, whereby actuation of the manually operable switch for a time period less than that of the delay circuit adds one signal to the seconds display and actuation of the manually operable switch for a greater time period adds one signal and thereafter blocks transmission of further signals to the seconds display for as long as the manually operable switch continues to be actuated.

2. Time-piece as set forth in claim 1 wherein the delay circuit comprises a second sequence of bistable devices.

3. Time-piece as set forth in claim 2 wherein a memory device is included in the second sequence in order to provide a continuous clamping signal to the first sequence during actuation of the switch after running of the delay period of the second sequence.

4. Time-piece as set forth in claim 2 wherein a selflatching circuit maintains the second sequence .in clamping conditions whilst providing a continuous clamping signal to the first sequence during actuation of the switch after running of the delay period of the second sequence.

5. Time-piece as set forth in claim 1 wherein a further manually operated switch is provided arranged and adapted to clamp a predetermined number of bistable devices in the first sequence immediately preceding the display control toggle thereby to facilitate exact setting of the phase of output signals to the display arrangement.

6. Time-piece as set forth in claim 1 wherein the display arrangement comprises a stepping motor arranged to drive time indicating hands.

7. Time-piece as set forth in claim 6 wherein the motor is driven by successive current pulses of opposite polarity. 

1. Time-piece in which a time standard supplies signals of a predetermined frequency to a first sequence of bistable devices arranged and adapted to provide output signals of a desired frequency to a display arrangement in which at least ''''seconds'''' are displayed, wherein means are provided to set the seconds display through the supplying of additional output signals or the withholding of output signals, said means including a complement output terminal on at least one of the bistable devices in the first sequence, a bistable storage device arranged to be manually switchable to a first stable state and to be automatically restored to a second stable state by signals obtained from the complement output terminal, a display control toggle having an input arrangement which logically combines said output signals from the first sequence of bistable devices with signals from the bistable storage device, a delay circuit having a controllable disabling switch and receiving an input from a predetermined bistable device in the first sequence in order to provide an output adapted to block signal transmission from at least one bistable device in the first sequence; and a manually operable switch coupled to the bistable storage device and the delay circuit disabling switch, whereby actuation of the manually operable switch for a time period less than that of the delay circuit adds one signal to the seconds display and actuation of the manually operable switch for a greater time period adds one signal and thereafter blocks transmission of further signals to the seconds display for as long as the manually operable switch continues to be actuated.
 2. Time-piece as set forth in claim 1 wherein the delay circuit comprises a second sequence of bistable devices.
 3. Time-piece as set forth in claim 2 wherein a memory device is included in the second sequence in order to provide a continuous clamping signal to the first sequence during actuation of the switch after running of the delay period of the second sequence.
 4. Time-piece as set forth in claim 2 wherein a self-latching circuit maintains the second sequence in clamping conditions whilst providing a continuous clamping signal to the first sequence during actuation of the switch after running of the delay period of the second sequence.
 5. Time-piece as set forth in claim 1 wherein a further manually operated switch is provided arranged and adapted to clamp a predetermined number of bistable devices in the first sequence immediately preceding the display control toggle thereby to facilitate exact setting of the phase of output signals to the display arrangement.
 6. Time-piece as set forth in claim 1 wherein the display arrangement comprises a stepping motor arranged to drive time indicating hands.
 7. Time-piece as set forth in claim 6 wherein the motor is driven by successive current pulses of opposite polarity. 